In printing operation of a digital image forming apparatus such as a full-color copying apparatus, data inputted from an image input apparatus such as a scanner is outputted to an image output apparatus such as an electrophotographic output engine or an inkjet output engine. In the printing operation, it is necessary that the digital image forming apparatus carry out image processing operation, so as to convert RGB data, which is supplied from the image input apparatus, into CMYK data or the like data compatible with the image output apparatus.
In the image processing operation, a huge amount of data is processed. Moreover, a high-speed real-time output is required, so as to catch up with operation of the image output apparatus. Therefore, in most cases, hard-wired ASICs (Application Specific Integrated Circuits) have been used in conventional hardware that performs the image processing operation.
However, thanks to recently improved capabilities of general-purpose processors and DSPs (Digital Signal Processors), it is now possible to perform the image processing operation by using software. Even under such a circumstance, problems will arise if a processor having only one processing section for executing instructions is used for carrying out the image processing operation for a digital image forming apparatus such as a full-color copying apparatus. This is because a capability of such a processor is insufficient. In many cases, therefore, the image processing operation is performed by using (i) an MIMD (Multiple Instruction, Multiple Data) type processor typified by an SIMD (Single Instruction, Multiple Data) type processor and a VLIW (Very Long Instruction Word) type processor, the MIMD type processor being such that a plurality of processing sections are mounted in a single processor element, (ii) a processor in which both the SIMD and the VLIW are used, or (iii) a multiprocessor system using a plurality of (i)/or (ii).
Incidentally, in case the image processing operation is performed as described above by using a processor having a plurality of processing sections or by using multiprocessors, there is a problem of division of the operation, i.e. a problem of determining which part of the operation is allocated to which computing unit.
In order to divide the operation, if the image processing operation is performed by using an SIMD type processor, it is necessary to divide data. This is because an SIMD type processor processes many sets of data in accordance with a single instruction.
Meanwhile, with the arrangements of an MIMD type processor and a multiprocessor, the image processing can be divided with respect to instructions or instruction groups. For example, Japanese Publication for Unexamined Patent Application, Tokukaihei 8-44678 (publication date: Feb. 16, 1996) (hereinafter “the first related art”) discloses a method in which data is processed after the data is divided in accordance with a load of each CPU.
The recently improved capabilities of general-purpose processors and DSPs are realized principally by increased scale of circuits that can be integrated, and by improvement of an operating speed. Meanwhile, the improved processing capabilities lead to a problem of increased power consumption. In response to this problem, for example, Japanese Publication for Unexamined Patent Application, Tokukai 2002-99433 (publication date: Apr. 5, 2002) (hereinafter “the second related art”) discloses a system that reduces power consumption by adjusting an operating frequency and a line voltage of each processor, so as to meet, at each moment during operation, requirements on each periodic real-time task under operation.
Moreover, Japanese Publication for Unexamined Patent Application, Tokukaihei 6-214961 (publication date: Aug. 5, 1994) (corresponding to U.S. Pat. No. 5,301,324, hereinafter “the third related art”) discloses an apparatus that performs reallocation dynamically by task-redirecting operation for an asymmetrical processor.
How to arrange a plurality of processing sections of a processor is an important factor. In the image processing operation, some processes (e.g. a table referring process) require a lot of memory, and some processes (e.g. an FIR (Finite Impulse Response) filtering process) are mostly about calculation. Moreover, in some processes in which one process is repeated (e.g. an FFT (Fast Fourier Transform) process), performance is drastically improved by using an exclusive instruction.
In light of the above, in an MIMD type processor arrangement or a multiprocessor arrangement, with which the image processing operation can be divided with respect to instructions or instruction groups, an asymmetrical processor arrangement is more advantageous than a symmetrical processor arrangement. This is because the asymmetrical processor arrangement, in which processing sections are arranged asymmetrically, require less hardware resources (e.g. memory, circuit size, and the like) for processors than the symmetrical processor arrangement does, in which each processing section or each processor equally has hardware resources (e.g. memory, instructions, and the like) that are necessary only for some processes.
In the asymmetrical multiprocessor arrangement, one processor is different from another processor in terms of hardware conditions, and the image processing operation as a whole is not carried out by using all the processors. Therefore, the method described in the first related art, that is, a method in which image data is divided and allocated to processing sections, cannot be employed.
Moreover, in many cases, the processors (image processing processors) for use in the image processing operation have a special arrangement for the image processing, so as to perform high-speed processing. In such cases, it is more efficient to use a general-purpose processor so as to perform sequence control and the like, such as a dispatch process for allocating jobs. However, in a multiprocessor arrangement in which a plurality of image processing processors are provided, if unit jobs to be allocated are determined in accordance with loads, as described in the third related art, the image processing processors do not operate while the dispatch is performed. As a result, a processing speed of the system as a whole is decreased.
Moreover, in the first related art, the process is divided only in light of processing capability, without considering power-consumption saving. On the other hand, in the second related art, processing capability necessary for each processor at each moment during operation is calculated, and power consumption is controlled in accordance with results of the calculations. However, because the calculations are performed with respect to each processor element, it is not considered in the power-consumption control that power consumption is different from one processor element to another. As a result, with this arrangement, power consumption of the asymmetrical multiprocessor cannot be saved sufficiently.